Memory devices have traditionally been accessed by a relatively standard set of control signals that are used by all manufacturers. For example, dynamic random access memories (DRAMs) have traditionally been accessed by a row address strobe (RAS) signal, a column address strobe (CAS) signal, a write enable (WE) signal, and a chip select (CS) signal. These signals were used to control the timing of the internal circuitry on the memory, and the memory generally performed asynchronously with respect to any other system clock signals. Recently, however, synchronous memory devices have become popular. In synchronous memory devices, the signals that previously controlled the timing of events inside the memory instead encode commands for various functions and are recognized by the memory synchronously with the system clock signal. Accesses to synchronous memory devices have required new memory controller designs.
For example, synchronous DRAMs (SDRAMs) recognize a set of commands that are encoded on the RAS, CAS, WE, and CS input signals, and typically on one or more address signals as well. SDRAM controllers recognize memory accesses to the SDRAMs and generate these signals in the appropriate sequence in response. In addition to recognizing accesses to the SDRAMs, the SDRAM controller also generates the appropriate combinations of signals to perform certain overhead functions. For example, after power up SDRAMs require all banks to be precharged. In addition SDRAMs typically have a mode register that allows the SDRAM to be configured for the particular system. Known SDRAM controllers perform these overhead functions by recognizing an access to a special memory-mapped location. However these approaches require extra address decode logic and can create "holes" in the address space that are then unavailable to other devices. In addition the circuitry for performing these overhead accesses has tended to be complex. What is needed is a controller for memories such as SDRAMs that is flexible but at the same time requires a minimum of extra circuitry to perform overhead accesses. Such a memory controller is provided by the present invention, whose features and advantages will be further described with reference to the drawings and the accompanying description.